1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and more particularly, the present invention relates to circuits and methods for generating a boosted voltage in a semiconductor memory device.
A claim of priority is made to Korean Patent Application No. 10-2005-0000802, filed on Jan. 5, 2005, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
2. Description of the Related Art
Semiconductor memory devices generally include a circuit which generates a boosted voltage which is greater than a power supply voltage. The boosted voltage is supplied to activate a word line in the semiconductor memory device. The word line is activated during row activation and/or during a refresh operation. In the refresh operation, the word lines of all memory banks in the semiconductor memory device are activated, thus resulting in high consumption of the boosted voltage.
Accordingly, more word lines are activated during the refresh operation than during row activation, which can result in noise in the boosted voltage.
FIG. 1 is a block diagram of a conventional circuit which generates a boosted voltage VPP in a semiconductor memory circuit. The circuit of FIG. 1 includes an active kicker 140 and a circuit 100 which generates a signal for driving the active kicker 140. In general, the boosted voltage VPP is supplied to a word line driver (not shown) to maintain a voltage of an activated word line with the boosted voltage VPP.
The circuit 100 is an automatic pulse generator which includes a first NOR gate 110, a second NOR gate 120, and a delay circuit 130. The delay circuit 130 includes an odd number of inverters INV1, INV2, and INV3. When a row active command or a fresh command is input to the circuit 100, the circuit 100 generates an active kicker drive pulse signal AKE in response to an active signal ACT. The pulse duration of the active kicker drive pulse signal AKE is the same as an inverter delay time T1 in the delay circuit 130, illustrated in FIG. 2.
In response to the active kicker drive pulse signal AKE, the active kicker 140 generates the boosted voltage VPP. The active kicker 140 is a well-known pumping circuit, and thus, a detailed description thereof will be omitted.
FIG. 2 is a timing diagram of an active kicker drive pulse signal AKE generated during row activation by the conventional circuit illustrated in FIG. 1. Referring to FIG. 2, an active signal ACT is generated in a semiconductor memory device in response to a row active command 210 among external commands COMMAND input to the semiconductor memory device. When the active signal ACT is activated at a logic high level, the active kicker drive pulse signal AKE is activated from a logic low level to a logic high level. Each pulse of the active kicker drive pulse signal AKE is maintained for a delay time T1, and deactivated at a logic low level. The active kicker 140 of FIG. 1 generates the boosted voltage VPP for the delay time T1.
The active signal ACT is deactivated at a logic low level in response to a precharge command 220 among the external commands COMMAND. In FIG. 2, tRC denotes a row active cycle that is a total duration in which the row active command 210, the precharge command 220, and the next row active command 230 are sequentially input to the semiconductor memory device.
In general, a word line in the semiconductor memory device is activated and deactivated in association with the active signal ACT, and a word line is activated during the row active cycle tRC. A pulse duration of the active kicker drive pulse signal AKE is designed to supply the boosted voltage VPP which is sufficient to activate a word line.
FIG. 3 is a timing diagram of an active kicker drive pulse signal AKE generated during a refresh operation by the conventional circuit of FIG. 1. Referring to FIG. 3, a refresh signal REF is generated in a semiconductor memory device in response to a refresh command 300 among external commands COMMAND input to the semiconductor memory device. When the refresh signal REF is activated at a logic high level, a refresh counter in the semiconductor memory device operates to sequentially generate cycle signals. The active signal ACT is activated in response to each of the cycle signals and deactivated after a predetermined length of time. The activation of the active signal ACT results in activation of the active kicker drive pulse signal AKE at a logic low level to a logic high level.
As illustrated in FIG. 2, during row activation, pulses of the active kicker drive pulse signal AKE are sequentially generated since the row active command 210 and the precharge command 229 are sequentially and individually input to the semiconductor memory device. In contrast, referring to FIG. 3, during the refresh operation, when the refresh command 300 is input to the semiconductor memory device, a refresh counter (not shown) in the semiconductor memory device activates each word line sequentially and repeatedly for a predetermined time, i.e., a refresh cycle tRFC. Each pulse of the active kicker drive pulse signal AKE is maintained for a delay time T1 during the refresh cycle tRFC. The refresh cycle tRFC is longer than the row active cycle tRC of FIG. 2.
When word lines in all memory banks are simultaneously activated during the refresh operation, a large amount of the boosted voltage VPP is consumed and a peak noise occurs in the boosted voltage VPP. The peak noise degrades the efficiency of a pumping circuit, such as an active kicker, which generates the boosted voltage VPP and may cause the refresh operation to be unstably performed.
A conventional circuit which generates a boosted voltage as illustrated in FIG. 1 generates an active kicker drive pulse signal AKE in both row activation and the refresh operation, and thus, there is a limit to improving the pumping efficiency of the circuit during the refresh operation.